Samsung S5PC100 User Manual page 442

S5PC100 USER'S MANUAL (REV1.0)
2.4 INITIALIZATION PROTOCOL
1) Power On
The controller is designed such that it requires a sequence for correct operation after all power to the
S5PC100 and to the memory devices is stable. The controller does not include circuitry to control the
activation of power and ground to the system. Once the power to the memory devices and the S5PC100 is
stable, the controller must be initialized.
The memory device is stable after 470us later than POR activation.
When the system is reset and enable special clock(CLK_GATE_SCLK_0[2]) and count done
Cold_Reset_Delay(refer to 4.1.33), the controller automatically reads certain registers in the flash memory
device and stores the values into the controller registers. If you want to skip Cold_Reset_Delay counting,
Write "0x00" to Cold_Reset_Delay SFR. To configure the system to use the flash memory devices, you must
read the following controller registers:
•
manufacturer_id
•
device_id
•
version_id
•
data_buffer_size
•
boot_buffer_size
•
amount_of_buffers
•
technology
2) Auto Configuration
After performing the power on sequence and enable special clock(CLK_GATE_SCLK_0[2]), the controller
automatically configures itself to work with the OneNAND Flash memory devices that are connected by
populating the following registers:
•
ddp_support
•
cache_read_support
•
sync_write
•
fba_width
•
fpa_width
•
fsa_width
•
device_page_size
•
single_page_buffer
If any of these parameters are incorrectly decoded for a new device, they are overwritten with the correct values
by software.
The register superload_support and cache_program_support must be set before issuing superload and cache
program command.
ONENAND CONTROLLER
5.3-5