Samsung S5PC100 User Manual page 423

DRAM CONTROLLER
4.2.22 PHY Test Register 1 (PhyTest1, R, Address=0xE600_005C)
PHYTEST1
ctrl_fb_cnt3 [31:24]
ctrl_fb_cnt2 [23:16]
ctrl_fb_cnt1 [15:8]
ctrl_fb_cnt0
4.2.23 Quality of Service Control Register n (QosControl n, R/W, Address=0xE600_0060 + 8n (n=0~7,
integer)
QOSCONTROLn
Reserved [31:28]
qos_cnt [27:16]
qos_en
5.1-40
Bit
Count value for data3 channel
Count value for data2 channel
Count value for data1 channel
[7:0] Count value for data0 channel
Bit
Should be zero
QoS Cycles
0xn = n aclk cycles
The matched ARID uses this value for its timeout counters
instead of ConControl.timeout_cnt.
QoS Enable
0x0 = Disable,
0x1 = Enable
[0]
If this function is enabled, its timeout counter works and the
ARID is masked with QoSConfig.qos_mask and compared
with QoSConfig.qos_id
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset
R/W
Value
R 0x0
R 0x0
R 0x0
R 0x0
Reset
R/W
Value
0x0
R/W 0x0
R/W 0x0