Samsung S5PC100 User Manual page 347

S5PC100 USER'S MANUAL (REV1.0)
Each counter must be synchronized to the other clock domain because the counters are updated in different
timing domains. The counters use a Gray code to ensure the safety of operation of the FIFOs, therefore the
synchronization always captures either:
•
Old value of the counter
•
New value of the counter.
It cannot capture an intermediate state because only one bit of the counter changes between adjacent Gray code
values. This ensures that if the old value is captured then the FIFO appears:
•
on the read side, to be emptier than it is, the write side seems to have written less than it has
•
on the write side, to be fuller than it is, the read side seems to have read less than it has.
In both cases, this indicates right-side failure that does not enable overflow or underflow. Subsequent
synchronization captures the new value. Figure 3.4-4 shows timing for a single place FIFO.
Each channel exhibits latency between two and three read-clock cycles from the write-clock edge on which the
data is accepted, and the earliest read-clock edge at which the data can be read. The latency experienced by any
particular transfer depends on the occupancy of the FIFO with the minimum only guaranteed when starting with
the FIFO in an empty state. The range of two to three cycles is because of the following:
•
The write-clock edge that is the start of the latency interval can occur anywhere in the read-clock cycle
•
The possibility of metastability in the synchronization process between the timing domains.
Sustained throughput in this mode cannot exceed that of the slower side. Based on the amount of buffering, the
short term throughput can appear significantly higher than the sustained rate.
Figure 3.4-4 Single Place FIFO Timing
ASYNC BRIDGE
3.4-5