Samsung S5PC100 User Manual page 597

PULSE WIDTH MODULATION TIMER
5.17 INTERRUPT CONTROL AND STATUS REGISTER (TINT_CSTAT, R/W, ADDRESS = 0XEA00_0044)
TINT_CSTAT
Reserved
Timer 4 Interrupt Status
Timer 3 Interrupt Status
Timer 2 Interrupt Status
Timer 1 Interrupt Status
Timer 0 Interrupt Status
Timer 4 interrupt Enable
Timer 3 interrupt Enable
Timer 2 interrupt Enable
Timer 1 interrupt Enable
Timer 0 interrupt Enable
7.1-20
Bit
[31:10] Reserved Bits
Timer 4 Interrupt Status Bit. Clears by writing '1' on
[9]
this bit.
Timer 3 Interrupt Status Bit. Clears by writing '1' on
[8]
this bit.
Timer 2 Interrupt Status Bit. Clears by writing '1' on
[7]
this bit.
Timer 1 Interrupt Status Bit. Clears by writing `1' on
[6]
this bit.
Timer 0 Interrupt Status Bit. Clears by writing '1' on
[5]
this bit.
Enables Timer 4 Interrupt.
[4]
1 = Enabled
0 = Disabled
Enables Timer 3 Interrupt.
[3]
1 = Enabled
0 = Disabled
Enables Timer 2 Interrupt.
[2]
1 = Enabled
0 = Disabled
Enables Timer 1 Interrupt.
[1]
1 = Enabled
0 = Disabled
Enables Timer 0 Interrupt.
[0]
1 = Enabled
0 = Disabled
S5PC100 USER'S MANUAL (REV1.0)
Description Reset Value
0x00000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0