Samsung S5PC100 User Manual page 152

CLOCK CONTROLLER
2 CLOCK DECLARATION
The clocks in S5C100 are classified into following:
•
Clocks from clock pads, i.e., XusbXTI, XXTI, XXTI27, and XrtcXTI
•
Clocks from a Clock Management Unit (CMU), e.g., HCLKD0, HCLKD1, and etc
•
Clocks from USB OTG PHY (refer 7.8)
•
Clocks from GPIO pads, e.g., XciPCLK, XpwmECLK, and etc
2.1 CLOCKS FROM CLOCK PADS
The following clocks are provided from clock pads. Crystal clock pads can be disabled.
•
USB_XI: Clock from a crystal pad with XusbXTI and XusbXTO pins. This clock is supplied to (A, E, M) PLLs
as well as an USB PHY. For more information on USB PHY clock, refer to "Section 7.8". Input frequency
range: 12 ~ 48MHz for supplying clock to USB PHY
•
OSC_IN: Clock from a crystal pad with XXTI and XXTO pins. If USB is not used at commercial set, CMU and
PLL use this clock to generate clocks to modules. Input frequency range: 12 ~ 20MHz
•
OSC27_IN: Cock from 27MHz a crystal pad with XXTI27 and XXTO27 pins. Clock doubler in CMU, HPLL,
and MIPI D-PHY use this clock. Clock doubler makes 54MHz clock (named, VCLK_54) for SD TV out. HPLL
usually makes 74.25 MHz for HD @60fps, and 74.176 MHz for HD @59.94fps. A PLL in MIPI D-PHY also
uses this clock to make MIPI clock (up-to 1GHz).
•
RTC_XT: Clock from a 32.768 KHz crystal pad with XrtcXTI and XrtcXTO pins. RTC can use this clock as the
source of a real time clock.
2.3-2
S5PC100 USER'S MANUAL (REV1.0)