Samsung S5PC100 User Manual page 208

S5PC100 USER'S MANUAL (REV1.0)
Power off status of each power domain is found in the BLK_PWR_STAT register. BLK_PWR_STAT is not
updated until the power-up or power-down process is completed. NORMAL_CFG and BLK_PWR_STAT have
different values while the power-up or power-down procedure is going on, and has the same value after the power
state change is completed. Look up the BLK_PWR_STAT register value to check the completion of power off.
If you want to power on or off each power domain(Sub/Audio), you should first write the corresponding bits of
NORMAL_CFG, and then you should check the power on/off status by reading the corresponding bits of
BLK_PWR_STAT register. After checking the power on/off status, you should proceed to the next action.
Note that Cortex-A8 is always ON in NORMAL mode.
3.3 IDLE MODE
If Cortex-A8 is not required to operate, the clock for Cortex-A8 can be disabled internally in order to save the
dynamic power consumption. This is done by executing a 'Wait For Interrupt' instruction. Except the state of
Cortex-A8 core, the remaining parts of the chip, keep their operating states in NORMAL, i.e., the running modules
are still running, clock-gated modules are still clock-gated, and powered-off modules are still power-off.
To enter IDLE mode:
1. Set CFG_STANDBYWFI field of PWR_CFG to 2'b01.
2. Set DEEP field register in CFG_DEEP_IDLE field of PWR_CFG to 1'b0.
3. Set PMU_INT_DISABLE bit of OTHERS register to 1'b1 to prevent interrupts from occurring while entering
IDLE mode.
4. Execute 'Wait For Interrupt' instruction (WFI).
To exit IDLE mode:
1. Various types of wakeup sources are used. Wakeup sources referred in Section 5 WAKEUP SOURCES.
3.4 DEEP-IDLE MODE
If Cortex-A8 is not required to operate, and for further reduction of CPU power, the power to Cortex-A8 core is off
internally in order to save the dynamic power consumption. Set registers (PWR_CFG) in PMU and execute a Wait
for Interrupt instruction.
There are two options in DEEP-IDLE mode.
First option is that the remaining parts of the chip, keep their states in NORMAL mode.
Second option for low-power MP3 playback, i.e., Top domain and Sub-domain is also power off, but Audio domain
is still power on.
Set TOP_LOGIC_ON_DIDLE field of PWR_CFG register in PMU to select this options, i.e., TOP domain can be
either power-on or power-off by the setting of TOP_LOGIC_ON_DIDLE field of PWR_CFG register before the
entry into IDLE mode.
• TOP_LOGIC_ON_DIDLE = 1'b1, Top domain (logic), Sub-domain (logic), and Audio domain (logic) keep their
states in NORMAL mode.
• TOP_LOGIC_ON_DIDLE = 1'b0, Top domain (logic) and Sub-domain (logic) is also power-off, but Audio
domain (logic) is still power on.
Power Management
2.4-9