Samsung S5PC100 User Manual page 435

S5PC100 USER'S MANUAL (REV1.0)
Field Bit
ByteEnable0 [3]
WaitEnable0 [2]
AddrMode0 [1]
DataWidth0 [0]
nWBE / nBE(for UB/LB) control for Memory Bank0
0 = UB/LB used (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = UB/LB not used (XrnWBE[1:0] is dedicated nBE[1:0]
Wait enable control for Memory Bank0
0 = Disables WAIT
1 = Enables WAIT
Select SMC ADDR Base for Memory Bank0
0 = SMC_ADDR is Half-word base address.
(SRAM_ADDR[20:0] ← HADDR[21:1])
1 = SMC_ADDR is byte base address
(SMC_ADDR[20:0] ← HADDR[20:0])
Note: If DataWidth0 is "0", SMC_ADDR is byte base address. (This bit is
ignored.)
Data bus width control for Memory Bank0
0 = 8-bit
1 = 16-bit
Description
STATIC MEMORY CONTROLLER
Reset Value
1
0
0
1
5.2-9