Samsung S5PC100 User Manual page 937

SD/MMC CONTROLLER
3 BLOCK DIAGRAM
INTREQ
System
Bus
(AHB)
AHB slave I/F
8.12-2
HCLK
Domain
SFR
Status
CMD
ARG
Control
DMA
controller
AHB master
Figure 8.12-1 HSMMC Block Diagram
BaseCLK
Clock Control
Line
Control
FIFO
Control
DPSRAM
S5PC100 USER'S MANUAL (REV1.0)
SDCLK
Domain
Status
RSP
CMDRSP
packet
Control
Control
Status
DATA
packet
Pad
I/F