Samsung S5PC100 User Manual page 405

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DRAM CONTROLLER
4.2.4 Memory Chip1 Configuration Register (MemConfig1, R/W, Address=0xE600_000C)
MEMCONFIG1
chip_base
[31:24]
chip_mask
[23:16]
chip_map
[15:12]
chip_col
[11:8]
chip_row
chip_bank
5.1-22
Bit
AXI Base Address
AXI base address [31:24] = chip_base,
For example, if chip_base = 0x28, then AXI base address of
chip1 becomes 0x2800_0000.
AXI Base Address Mask
Upper address bit mask to determine AXI offset address of
memory chip1.
0 = Corresponding address bit is not to be used for comparison
1 = Corresponding address bit is to be used for comparison
This bit field is used to check whether 'accessed address' &
'mask address' is equal to 'base address'. For example, if
chip_mask = 0xF8, then AXI offset address becomes
0x0000_0000 ~ 0x07FF_FFFF. If AXI base address of memory
chip1 is 0x2800_0000, then memory chip1 has an address
range of 0x2800_0000 ~ 0x2FFF_FFFF.
Address Mapping Method (AXI to memory)
0x0 = Linear ({bank, row, column, width}),
0x1 = Interleaved ({row, bank, column, width}),
0x2 ~ 0xf = Reserved
Number of Column Address Bits
0x0 = 7 bits,
0x1 = 8 bits,
0x2 = 9 bits,
0x3 = 10 bits,
0x4 ~ 0xf = Reserved
Number of Row Address Bits
0x0 = 12 bits,
0x1 = 13 bits,
[7:4]
0x2 = 14 bits,
0x3 = 15 bits,
0x4 ~ 0xf = Reserved
Number of Banks
0x0 = 1 bank,
0x1 = 2 banks,
[3:0]
0x2 = 4 banks,
0x3 = 8 banks,
0x4 ~ 0xf = Reserved
S5PC100 USER'S MANUAL (REV1.0)
Description
Reset
R/W
Value
R/W
0x28
R/W
0xF8
R/W
0x0
R/W
0x3
R/W
0x1
R/W
0x2

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