Samsung S5PC100 User Manual page 676

S5PC100 USER'S MANUAL (REV1.0)
4.2.6 SPI Status Register
•
SPI_STATUS0, R, Address = 0xEC30_0014
•
SPI_STATUS1, R, Address = 0xEC40_0014
•
SPI_STATUS2, R, Address = 0xEC50_0014
SPI_STATUSn
TX_DONE
TRAILING_BYTE
RX_FIFO_LVL
TX_FIFO_LVL
RX_OVERRUN
RX_UNDERRUN
TX_OVERRUN
TX_UNDERRUN
RX_FIFO_RDY
TX_FIFO_RDY
Bit
Indication of transfer done in Shift register(master mode only)
[21] 0 = All case except blow case
1 = If Tx FIFO and shift register are empty
[20] Indication that trailing count is 0
Data level in RX FIFO
[19:13]
0 ~ 64 byte
Data level in TX FIFO
[12:6]
0 ~ 64 byte
Rx Fifo overrun error
[5]
0 = No Error,
Rx Fifo underrun error
[4]
0 = No Error,
Tx Fifo overrun error
[3]
0 = No Error,
Tx FIFO underrun error
Tx FIFO underrun error is occurred if TX FIFO is empty in slave
[2]
mode.(no empty state in slave Tx mode)
0 = No Error,
0 = Data in FIFO less than trigger level
[1]
1 = Data in FIFO more than trigger level
0 = Data in FIFO more than trigger level
[0]
1 = Data in FIFO less than trigger level
Description
1 = Overrun Error
1 = Underrun Error
1 = Overrun Error
1 = Underrun Error
SPI CONTROLLER
Reset Value
0
0
0
0
0
0
0
0
0
0
8.3-11