Samsung S5PC100 User Manual page 592

S5PC100 USER'S MANUAL (REV1.0)
5.2 TIMER CONFIGURATION REGISTER (TCFG1, R/W, ADDRESS = 0XEA00_0004)
TCFG1
Reserved
Divider MUX4
Divider MUX3
Divider MUX2
Divider MUX1
Divider MUX0
NOTE: If you use PWM_TCLK, duty of TOUT may show slight error. PWM_TCLK is sampled by PCLK in PWM
module.
But PWM_TCLK and PCLK is asynchronous clock. Therefore PWM_TCLK is not sampled at exact time. This slight
error can be reduced if PWM_TCLK is slower than PCLK. Therefore we recommend to use PWM_TCLK under
1MHz.
(For Example: If PCLK is 66MHz and PWM_TCLK is 1MHz, duty error is 1.5%. If PCLK is 66MHz and
PWM_TCLK is 0.5MHz, duty error is 0.75%)
Bit
[31:24] Reserved Bits
Selects Mux input for PWM Timer 4
0000 = 1/1
0001 = 1/2
[19:16]
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = PWM_TCLK
Selects Mux input for PWM Timer 3
0000 = 1/1
0001 = 1/2
[15:12]
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = PWM_TCLK
Selects Mux input for PWM Timer 2
0000 = 1/1
0001 = 1/2
[11:8]
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = PWM_TCLK
Selects Mux input for PWM Timer 1
0000 = 1/1
0001 = 1/2
[7:4]
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = PWM_TCLK
Selects Mux input for PWM Timer 0
0000 = 1/1
0001 = 1/2
[3:0]
0010 = 1/4
0011 = 1/8
0100 = 1/16
0101 = PWM_TCLK
PULSE WIDTH MODULATION TIMER
Description Reset Value
0x00
0x00
0x00
0x00
0x00
0x00
7.1-15