Samsung S5PC100 User Manual page 657

S5PC100 USER'S MANUAL (REV1.0)
1.5 READ-WRITE OPERATION
In Transmitter mode, if the data is transferred, the I
receives a new data. Before the new data is written into the register, the SCL line is held low, and then released
after it is written. The S5PC100 holds the interrupt to identify the completion of current data transfer. After the
CPU receives the interrupt request, it writes a new data into the I2CDS register, again.
In Receive mode, if data is received, the I
is read out, the SCL line is held low and then released after it is read. The S5PC100 holds the interrupt to identify
the completion of the new data reception. After the CPU receives the interrupt request, it reads the data from the
I2CDS register.
1.6 BUS ARBITRATION PROCEDURES
Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with
a SDA High level detects the other master with a SDA active Low level, it does not initiate a data transfer because
the current level on the bus does not correspond to its own. The arbitration procedure extends until the SDA line
turns High.
If the masters simultaneously lower the SDA line, each master evaluates whether the mastership is allocated itself
or not. For the purpose of evaluation each master detects the address bits. While each master generates the
slaver address, it detects the address bit on the SDA line because the SDA line is likely to get Low rather than to
keep High. Assume that one master generates a Low as first address bit, while the other master is maintaining
High. In this case, both masters detect Low on the bus because the Low status is superior to the High status in
power. If this happens, Low (as the first bit of address) generating master gets the mastership while High (as the
first bit of address) generating master withdraws the mastership. If both masters generate Low as the first bit of
address, there is arbitration for the second address bit, again. This arbitration continues to the end of last address
bit.
1.7 ABORT CONDITIONS
If a slave receiver cannot acknowledge the confirmation of the slave address, it holds the level of the SDA line
High. In this case, the master generates a Stop condition and to abort the transfer.
If a master receiver is involved in the aborted transfer, it signals the end of the slave transmit operation by
canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter
releases the SDA to allow a master to generate a Stop condition.
2
C-BUS
1.8 CONFIGURING I
To control the frequency of the serial clock (SCL), the 4-bit prescaler value is programmed in the I2CCON
2
register. The I C-bus interface address is stored in the I
interface address has an unknown value).
1.9 FLOWCHARTS OF OPERATIONS IN EACH MODE
The following steps must be executed before any I
1. Write own slave address on I2CADD register, if needed.
2. Set I2CCON register.
a) Enable interrupt
b) Define SCL period
3. Set I2CSTAT to enable Serial Output
2
C-bus interface waits until I
2
C-bus interface waits until I2CDS register is read. Before the new data
2
C-bus address (I2CADD) register (By default, the I
2
C Tx/Rx operations.
2
I C-BUS INTERFACE
2
C-bus Data Shift (I2CDS) register
2
C-bus
8.2-5