Samsung S5PC100 User Manual page 125

S5PC100 USER'S MANUAL (REV1.0)
5.5.72 Non wake-up Interrupt 11 Mask Register (NWU_INT11_MASK, R/W, Address = 0xE030_092C)
Field
Reserved
NWU_INT11_MASK[n]
5.5.73 Non wake-up Interrupt 12 Mask Register (NWU_INT12_MASK, R/W, Address = 0xE030_0930)
Field
Reserved
NWU_INT12_MASK[n]
5.5.74 Non wake-up Interrupt 13 Mask Register (NWU_INT13_MASK, R/W, Address = 0xE030_0934)
Field
Reserved
NWU_INT13_MASK[n]
5.5.75 Non wake-up Interrupt 14 Mask Register (NWU_INT14_MASK, R/W, Address = 0xE030_0938)
Field
Reserved
NWU_INT14_MASK[n]
5.5.76 Non wake-up Interrupt 15 Mask Register (NWU_INT15_MASK, R/W, Address = 0xE030_093C)
Field
Reserved
NWU_INT15_MASK[n]
5.5.77 Non wake-up Interrupt 16 Mask Register (NWU_INT16_MASK, R/W, Address = 0xE030_0940)
Field
Reserved
NWU_INT16_MASK[n]
5.5.78 Non wake-up Interrupt 17 Mask Register (NWU_INT17_MASK, R/W, Address = 0xE030_0944)
Field
Reserved
NWU_INT17_MASK[n]
Bit
[31:8] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,7)
Bit
[31:3] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,2)
Bit
[31:7] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,6)
Bit
[31:7] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,6)
Bit
[31:8] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,7)
Bit
[31:8] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,7)
Bit
[31:5] Reserved
[n] 0 = Enabled, 1 = Masked (n=0,..,4)
Description
Description
Description
Description
Description
Description
Description
PAD CONTRL
Reset Value
0
1
Reset Value
0
1
Reset Value
0
1
Reset Value
0
1
Reset Value
0
1
Reset Value
0
1
Reset Value
0
1
2.2-73