Samsung S5PC100 User Manual page 775

S5PC100 USER'S MANUAL (REV1.0)
DSIM_CLKCTRL
ByteClkSrc
ByteClkEn
LaneEscClkEn
Reserved
EscPrescaler
Bit
[26:25] Byte clock source selection
00 = D-PHY PLL (default)
01 = External Bit clock source and ByteClk source by
dividing by 4.
1X = External clock bypass to ByteClk
If you want to change clock source, turn off D-PHY PLL
before changing clock source.
If bit[1] is 1'b1, this case is used that MIPI DSIM transfer
data through LPDT mode only. In this case, it turns off
PLL and cannot generate bit clock.
If bit[1] is 1'b0 and bit[0] is 1'b1, External clock source is
used bit clock and ByteClk source. Generates ByteClk
by dividing 4 in MIPI DSIM clock generation module.
[24] Byte clock enabler
0 = Disables
1 = Enables
[23:19] Escape clock enabler for D-phy Lane
LaneEscClkEn[0] = Clock lane
LaneEscClkEn[1] = Data lane 0
LaneEscClkEn[2] = Data lane 1
LaneEscClkEn[3] = Data lane 2
0 = Disables
1 = Enables
[18:16] Reserved
[15:0] Escape clock prescaler value.
Escape clock frequency range is up to 20MHz. Note that
the requirement for BTA is Host Escclk frequency is
66.7 ~ 150% of Peripheral escape clock frequency.
EscClk = ByteClk / (2 * EscPrescaler)
Description
MIPI DSIM
R/W Reset Value
R/W 0
R/W 0
R/W 0
- -
R/W 0xFFFF
8.7-19