Samsung S5PC100 User Manual page 763

S5PC100 USER'S MANUAL (REV1.0)
1.3.2 Interface Timing and Protocol
1.3.2.1 Display Controller Interface
MIPI DSI Master has two-display controller interface: RGB I/F for main display and CPU I/F (I80 I/F) for main/sub
display. Video mode uses RGB I/F,and Command mode uses CPU I/F.
The RGB image data is loaded on the data bus of RGB I/F and I80 I/F with the same order : RGB_VD[23:0] or
SYS_VDOUT[23:0] is {R[7:0],G[7:0],B[7:0]}. Each byte aligns to the most significant bit. For instance, in 12-bit
mode, only three 4-bit values, i.e. data[23:20], data[15:12], and data[7:4], are valid as R,G, and B each. The DSIM
ignores rest of the bits.
1.3.2.2 RGB I/F
Vsync, Hsync and VDEN have to be active high signals.
Vsync and Hsync is pulse type that spends several video clocks.
RGB_VD[23:0] is {R[7:0],G[7:0],B[7:0]}.
All sync signals are synchronized to rising edge of RGB_VCLK.
Display controller has to send minimum 1 horizontal line length of Vsync pulse, V back porch, and V front porch.
Hsync pulse width should be longer than 1-byte clock cycle.
1.3.2.3 HSA Mode
HSA mode is Horizontal Sync Pulse areadisable mode.
Non burst mode
with Sync pulses
(HSAmode)
Figure 8.7-5 Block Timing Diagram of HSA Mode (HSA mode reset : DSIM_CONFIG[20] = 0)
Non burst mode
with Sync pulses
(HSAmode)
Figure 8.7-6 Block Timing Diagram of HSA mode (HSA mode set : DSIM_CONFIG[20] = 1)
HS
RGB
HBP
A
Hsync start packet
Hsync end packet
RGB
HBP
Hsync start packet
Hsync end packet
HS
HFP HBP
A
HFP HBP
MIPI DSIM
RGB
HFP
RGB
HFP
8.7-7