Samsung S5PC100 User Manual page 183

S5PC100 USER'S MANUAL (REV1.0)
10.2.3 Select Clock Source 2 (Multimedia and Connectivity) (CLK_SRC2, R/W, Address = 0xE010_0208)
Multimedia and Connectivity clock source register.
CLK_SRC2
Reserved
MIXER_SEL
Reserved
FIMC2_SEL
Reserved
FIMC1_SEL
Reserved
FIMC0_SEL
Reserved
LCD_SEL
Reserved
MMC2_SEL
Reserved
MMC1_SEL
Reserved
MMC0_SEL
Restriction: 54MHz (VCLK_54) clock is used for FIMCs and LCD, pass clock at least one among SCLK_HDMI,
SCLK_MIXER, and SCLK_VDAC54. (Refer CLK_GATE_SCLK_1 SFR)
Bit
[31:30] Reserved
Control MUX
(00:CLK27M, 01: VCLK_54, 10: MOUT
[29:28]
To run HDMI, set MIXER clock source as 10 (MOUT
[27:26] Reserved
Control MUX
[25:24]
(00:MOUT
EPLL
[23:22] Reserved
Control MUX
[21:20]
(00:MOUT
EPLL
[19:18] Reserved
Control MUX
[17:16]
(00:MOUT
EPLL
[15:14] Reserved
Control MUX
[13:12]
(00:MOUT
EPLL
[11:10] Reserved
Control MUX
[9:8]
(00:MOUT
EPLL
[7:6] Reserved
Control MUX
[5:4]
(00:MOUT
EPLL
[3:2] Reserved
Control MUX
[1:0]
(00:MOUT
EPLL
Description
, which is the source clock of MIXER
MIXER
, which is the source clock of FIMC2
FIMC2
, 01: DOUT , 10: MOUT
MPLL
, which is the source clock of FIMC1
FIMC1
, 01: DOUT , 10: MOUT
MPLL
, which is the source clock of FIMC0
FIMC0
, 01: DOUT , 10: MOUT
MPLL
, which is the source clock of LCD
LCD
, 01: DOUT , 10: MOUT
MPLL
, which is the source clock of MMC2
MMC2
, 01: DOUT , 10: FIN
MPLL
, which is the source clock of MMC2
MMC1
, 01: DOUT , 10: FIN
MPLL
, which is the source clock of MMC2
MMC0
, 01: DOUT , 10: FIN
MPLL
CLOCK CONTROLLER
)
HPLL
)
HPLL
11: VCLK_54)
HPLL,
11: VCLK_54)
HPLL,
11: VCLK_54)
HPLL,
11: VCLK_54)
HPLL,
, 11: MOUT )
EPLL HPLL
, 11: MOUT )
EPLL HPLL
)
EPLL
Reset Value
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
2.3-33