Samsung S5PC100 User Manual page 824

USB HOST CONTROLLER
5.2.9 USB HcControlHeadED Register (UHCHDED, Address = 0xED40_0020)
The UHCHDED register contains the physical address of the current Endpoint Descriptor of the control list. The
register organization and individual bit definitions are shown in Table 8.9-10. All reserved bits are read as 0 and
are unaffected by writes.
UHCHDED Bit
CHED [31:4]
- [3:0]
5.2.10 USB HcControlCurrentED Register (UHCCONCURRED, Address = 0xED40_0024)
The UHCCONCURRED register contains the physical address of the current Endpoint Descriptor of the control
list. The register organization and individual bit definitions are shown in Table 8.9-11. All reserved bits are read as
0 and are unaffected by writes.
8.9-24
Table 8.9-9 UHCHDED Bit Definitions
ControlHead Endpoint Descriptor
The UHC traverses the control list starting with the
HcControlHeadED pointer (the UHCCHED register); the
content is loaded from the HCCA during the initialization of
the UHC. This address pointer is 32 byte aligned, therefore,
the lower 4 bits are always 0.
Fixed at 0
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R/W
R