Samsung S5PC100 User Manual page 817

S5PC100 USER'S MANUAL (REV1.0)
5.2.4 USB HcInterruptStatus Register (UHCINTSTAT, Address = 0xED40_000C)
The USB INTerrupt STATus (UHCINTSTAT) register provides status on various events that cause hardware
interrupts. If an event occurs, the host controller sets the corresponding bit in this register. If a bit is set, a
hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register and the
MasterInterruptEnable bit is set. The host controller driver clears specific bits in this register by writing 1 to bit
positions to be cleared. The host controller driver cannot set any of these bits. The host controller never clears
these bits (except for during a system reset). Because of the difference in clock frequencies between the system
bus and the USB host controller core, there is latency from the time a write occurs on the system bus until the
actual register bit is cleared. The HCD needs to take into this delay into consideration.
*C; To clear this bit, write 1'b1 to it.
UHCINTSTAT Bit
Reserved [31]
OC [30]
Reserved [29:7]
RHSC [6]
FNO [5]
Table 8.9-4 UHCINTSTAT Bit Definitions
Description
Reserved
OwnershipChange
This bit is set by UHC if the host controller driver sets
the OwnershipChangeRequest field in
HcCommandStatus. However, this implementation of
the OHCI host does not support SMI. Therefore,
software must never write 1'b1 to the
UHCCOMSTAT[OCR] bit. This bit is tied to 0 because
the SMI pin is not implemented in this design.
Reserved
RootHubStatusChange
This bit is set if the content of HcRhStatus or the content
of any of HcRhPortStatus for port 1 and 2 has changed.
0 = The contents of the above four registers has not
changed.
1 = The contents of HcRhStatus or HcRhPortStatus[2:1]
has changed.
FrameNumberOverflow
This bit is set if the most significant bit (15) of
HcFmNumber changes value, from 0 to 1 or from 1 to 0,
and after HccaFrameNumber has been updated.
0 = Otherwise
1 = HcFmNumber (bit 15) changed in value, from 0 to 1
or from 1 to 0, or HccaFrameNumber has been updated
USB HOST CONTROLLER
R/W Reset Value
-
R/WC
-
R/WC
R/WC
8.9-17