Samsung S5PC100 User Manual page 821

S5PC100 USER'S MANUAL (REV1.0)
5.2.6 USB HcInterruptDisable Register (UHCINTDISB, R/W, Address = 0xED40_0014)
Each disable bit in the UHC Interrupt Disable (UHCINTDISB, shown in Table 8.9-7) register corresponds to an
associated interrupt bit in UHCINTSTAT, the UHC Interrupt Status register. The UHC Interrupt Disable register is
coupled with the UHC Interrupt Enable register. Thus, writing a 1 to a bit in this register clears the corresponding
bit in the UHC Interrupt Enable register, whereas writing a 0 to a bit in this register leaves the corresponding bit in
the UHC Interrupt Enable register unchanged. On a Read, the current value of the UHC Interrupt Enable register
is returned.
UHCINTDIS Bit
B
MIE [31]
OC [30]
Reserved [29:7]
RHSC [6]
FNO [5]
UE [4]
RD [3]
SF [2]
WDH [1]
Table 8.9-6 UHCINTDISB Bit Definitions
Master Interrupt Enable
0 = Ignore
1 = Disables interrupt generation due to events specified in
the other bits of this register.
This field is set after a hardware or software reset
Ownership Change
0 = Ignore
1 = Disables interrupt generation due to ownership change.
Reserved
Root Hub Status Change
0 = Ignore
1 = Disables interrupt generation due to root hub status
change.
Frame Number Overflow
0 = Ignore
1 = Disables interrupt generation due to frame number
overflow.
Unrecoverable Error
0 = Ignore
1 = Disables interrupt generation due to unrecoverable
error.
Resume Detect
0 = Ignore
1 = Disables interrupt generation due to resume detect.
Start of Frame
0 = Ignore
1 = Disables interrupt generation due to start of frame.
Writeback HcDoneHead
0 = Ignore
Description
USB HOST CONTROLLER
R/W Reset Value
R/W
R/W
-
R/W
R/W
R/W
R/W
R/W
R/W
8.9-21