Samsung S5PC100 User Manual page 225

Power Management
The behavior of EPLL in the other power down modes, is the same as the other PLLs (APLL, MPLL, HPLL).
The initial-state of S5PC100 after wake-up from the SLEEP mode is almost the same as the Power-On-Reset
state except for the contents of the external DRAM is preserved.
On the other hand, S5PC100 automatically recovers the previous working state after wake-up from the STOP
mode, and DEEP-STOP (top domain on).
Finally, after wake-up from the DEEP-IDLE (top domain off), DEEP-STOP (top domain off) and SLEEP mode, s/w
should recover the previous working state by using preserved information.
Mode before wake-up
IDLE
DEEP-IDLE
(Top domain on)
DEEP-IDLE
(Top domain off)
STOP
DEEP-STOP
(Top domain on)
DEEP-STOP
(Top domain off)
SLEEP
6.7 DAC
DAC has two power modes: Run and Power-down mode
• In Run mode, DAC sends and receives data normally.
• In Power-down mode, all power to DAC is off internally.
In NORMAL mode, both power modes can be used.
If DAC is in use, then it is in Run mode.
If DAC is not in use, it enters into Power-down mode to save static power by setting register in TVOUT logic.
In IDLE mode and DEEP-IDLE mode (top domain on), DAC keeps its operation or power state in NORMAL.
Before it enters to DEEP-IDLE mode (top domain off), STOP and DEEP-STOP, it is recommended that DAC
enters into Power-down mode.
Before it enters to SLEEP mode, power to DAC should be off to prevent leakage current.
2.4-26
Table 2.4-9 Status of PLLs and ARMCLK/HCLK after Wake-Up
APLL/MPLL/HPLL
on/off after wake up
unchanged
unchanged
off → off
off → on (by H/W)
off → on (by H/W)
off → off
off → off
S5PC100 USER'S MANUAL (REV1.0)
EPLL on/off after
wakeup
unchanged
unchanged
unchanged
off → on (by H/W)
off → on (by H/W)
off → off
off → off
HCLK after wakeup
PLL Output
PLL Output
PLL reference clock
PLL Output
PLL Output
PLL reference clock
PLL reference clock