Samsung S5PC100 User Manual page 205

Power Management
3 SYSTEM POWER MODE
3.1 OVERVIEW
According to the power saving schemes and features explained in the "Section 2 FUNCTION DESCRIPTION",
S5PC100 provides six power modes: NORMAL, IDLE, DEEP-IDLE, STOP, DEEP-STOP, and SLEEP.
Power modes are summarized in Table 2.4-3.
In NORMAL mode, use module-based clock off, block-based power off and frequency scaling to reduce power
consumption.
Based on operating scenario clock off reduces dynamic power consumption by disabling clock input to specific
module. Clock off can be done in module-by-module basis.
Power off reduces static power consumption of a block or power domain (a group of modules) by disconnecting a
leakage-current path. Power off can be done in block-by-block basis.
Frequency scaling reduces dynamic power consumption by lowering operating frequency.
In IDLE mode, CPU clock is disabled internally by entering Standby mode of Cortex-A8. CPU enters into Standby
mode by performing WFI instruction. In this mode, Cortex-A8 core is not running, therefore dynamic power of CPU
is reduced. The remaining parts of the chip keep their states in NORMAL mode. That is, clock-off modules are still
clock-off, and power-off domains are still power-off.
In DEEP-IDLE mode, Cortex-A8 core is power-off rather than clock-off. In DEEP-IDLE mode, CPU cores leakage
power is minimized. There are two options in DEEP-IDLE mode.
One option is that the remaining parts of the chip keep their states in NORMAL mode.
Second option is that for low-power MP3 playback, Top domain is power-off and Sub-domain except Audio
domain is power-off whereas Audio domain is still power on.
Set TOP_LOGIC_ON_DIDLE field of PWR_CFG register in PMU to select the above mentioned options, i.e., TOP
domain can either power-on or power-off by the setting of TOP_LOGIC_ON_DIDLE field of PWR_CFG register
before it enters into IDLE mode.
• TOP_LOGIC_ON_DIDLE = 1'b1, Top domain, Sub-domain, and Audio domains keep their states in NORMAL
mode.
• TOP_LOGIC_ON_DIDLE = 1'b0, Top domain and Sub-domain are power-off, but Audio domain is still
running.
As you can see, 'DEEP' means that Cortex-A8 Core is power-off.
In STOP mode, clocks to all modules except RTC are disabled, PLLs are disabled, and unnecessary oscillators
are selectively disabled to minimize dynamic power consumption. In this mode, Cortex-A8 Core enters into
Standby mode.
In DEEP-STOP mode, Cortex-A8 Core is power-off rather than clock-off as in STOP mode, and the remaining
parts of the chip are power-off except TOP, RTC, and ALIVE module. But TOP domain can be either power-on or
power-off by the setting of TOP_LOGIC_ON field of STOP_CFG register before it enters into DEEP-STOP mode.
Cortex-A8 L2 cache is powered on for memory retention, or power-off to save power.
• TOP_LOGIC_ON = 1'b1, Top domain, Sub-domain, and Audio domains are clock-off.
• TOP_LOGIC_ON = 1'b0, Top domain, Sub-domain, and Audio domains are power-off.
2.4-6
S5PC100 USER'S MANUAL (REV1.0)