Samsung S5PC100 User Manual page 268

S5PC100 USER'S MANUAL (REV1.0)
10.5.14 CLKDIV_IEM_L1-7 Register
• Clock Divider for IEM (Performance Level -7) (CLKDIV_IEM_L7, R/W, Address = 0xE010_8704)
• Clock Divider for IEM (Performance Level -6) (CLKDIV_IEM_L6, R/W, Address = 0xE010_8708)
• Clock Divider for IEM (Performance Level -5) (CLKDIV_IEM_L5, R/W, Address = 0xE010_870C)
• Clock Divider for IEM (Performance Level -4) (CLKDIV_IEM_L4, R/W, Address = 0xE010_8710)
• Clock Divider for IEM (Performance Level -3) (CLKDIV_IEM_L3, R/W, Address = 0xE010_8714)
• Clock Divider for IEM (Performance Level -2) (CLKDIV_IEM_L2, R/W, Address = 0xE010_8718)
• Clock Divider for IEM (Performance Level -1) (CLKDIV_IEM_L1, R/W, Address = 0xE010_871C)
Each register of CLKDIV_IEM_L1-7 configures clock divider values for ARM and HPM clocks at IEM performance
level from 1 to 7. The description of each field is the same as that of CLKDIV_IEM_L8 register.
CLKDIV_IEM_L1-7
Reserved
Reserved
pll_div_val_l1-7
Reserved
hpm_div_val_l1-7
Reserved
arm_div_val_l1-7
Reserved
bus_div_val_l1-7
Bit
[31:16] Reserved
[15:13] Reserved
This field is used to set dividing value in both DIV
DIV
APLL_HPM.
DIV clock divider ratio, DOUT
APLL
[12] (RATIO = pll_div_val_l1-7 + 1), and
DIV clock divider ratio, DOUT
APLL_HPM
RATIO (RATIO = pll_div_val_l1-7 + 1) at IEM performance
level from 1 to 7
[11] DO NOT CHANGE
This field is used only in closed-loop mode (by using HPM).
DIV clock divider ratio, SCLK_HPM = DOUT
HPM
[10:8]
RATIO (RATIO = hpm_div_val_l1-7 + 1) at IEM performance
level from 1 to 7
[7] DO NOT CHANGE
This field is used to set dividing value in both DIV
DIV
ARM_HPM.
DIV clock divider ratio, DOUT
ARM
[6:4] (RATIO = arm_div_val_l1-7 + 1), and
DIV clock divider ratio, DOUT
ARM_HPM
/ RATIO (RATIO = arm_div_val_l1-7 + 1), at IEM
performance level from 1 to 7
[3] DO NOT CHANGE
DIV clock divider ratio, HCLKD0 = DOUT
D0_BUS
[2:0] (RATIO = bus_div_val_l1-7 + 1) at IEM performance level
from 1 to 7
Description
= MOUT
APLL APLL
= MOUT
APLL_HPM
= DOUT
ARM APLL
= DOUT
ARM_HPM
ARM
Power Management
Reset Value
0x0000
000
and
APLL
/ RATIO
/
APLL
/
ARM_HPM
000
and
ARM
/ RATIO
000
APLL_HPM
/ RATIO
010
0
0
0
0
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