Samsung S5PC100 User Manual page 914

S5PC100 USER'S MANUAL (REV1.0)
DIEPCTLn/ Bit
DOEPCTLn
CNAK [26]
TxFNum [25:22] TxFIFO Number
Stall [21]
Snp [20]
EPType [19:18] Endpoint Type
NAKsts [17]
a Transfer Complete interrupt, or after a SETUP packet is
received on that endpoint.
Clear NAK
Applies to IN and OUT endpoints. A write to this bit clears the
NAK bit for the endpoint.
Applies to IN endpoints only.
Non-periodic endpoints must set this bit to zero. Periodic
endpoints must map this to the corresponding Periodic TxFIFO
number.
• 4'h0 : Non-Periodic TxFIFO
• Others : Specified Periodic TxFIFO number
Note: An interrupt IN endpoint could be configured as a non-
periodic endpoint for applications like mass storage.
STALL Handshake
Applies to non-control, non-isochronous IN and OUT endpoints
only. The application sets this bit to stall all tokens from the USB
host to this endpoint. If a NAK bit, Global Non-Periodic In NAK, or
Global OUT NAK is set along with this bit, the STALL bit takes
priority. Only the application clears this bit, never the core.
Applies to control endpoints only
The application sets this bit, and the core clears it, if a SETUP
token is received for this endpoint. If a NAK bit, Global Non-
Periodic IN NAK, or Global OUT NAK is set along with this bit, the
STALL bit takes priority. Irrespective of this bit's setting, the core
always responds to SETUP data packets with an ACK
handshake.
Snoop Mode
Applies to OUT endpoints only.
This bit configures the endpoint to Snoop mode. In Snoop mode,
the core does not check the correctness of OUT packets before
transferring them to application memory.
Applies to IN and OUT endpoints.
This is the transfer type supported by this logical endpoint.
• 2'b00 : Control
• 2'b01 : Isochronous
• 2'b10 : Bulk
• 2'b11 : Interrupt
NAK Status
Applies to IN and OUT endpoints.
Indicates the following:
• 1'b0: The core is transmitting non-NAK handshakes based on
the FIFO status
• 1'b1: The core is transmitting NAK handshakes on this
endpoint.
If either the application or the core sets this bit:
Description
USB2.0 HS OTG
R/W Reset
Value
W 1'b0
R/W 4'h0
R/W 1'b0
R_WS
_SC
R/W 1'b0
R 2'h0
R 1'b0
8.10-71