Samsung S5PC100 User Manual page 305

S5PC100 USER'S MANUAL (REV1.0)
5.3.13 APC Undershoot Threshold and Noise Limit Register (APC_UNSHT_NOISE, R/W, Address =
0xE100_0034)
APC_UNSHT_NOISE
Reserved
Noise Limit for
VDDOK
Undershoot Threshold
Level
5.3.14 Wakeup Delay Register (APC_WKUP_DLY, R/W, Address = 0xE100_0038)
APC_WKUP_DLY
Wakeup Delay
5.3.15 Slack Sample Count Register (APC_SLK_SMP, R/W, Address = 0xE100_003C)
APC_SLK_SMP
Reserved
Slack Sample Count
5.3.16 PWI Clock Division Register (APC_CLKDIV_PWICLK, R/W, Address = 0xE100_0040)
APC_CLKDIV_PWICLK
Reserved
Programmable Clock
Division
Bits
[7:6] Read undefined. Write as zero.
[5:4] Noise limit for the VDDOK generation due to the power
supply regulation errors. Provides the acceptable integrated
eHPM (+ve) below the RCC value for updating the
performance level in the closed-loop mode.
APC_UNSHT_NOISE[5:4]
[3:0] This is the threshold level for the detection of voltage
undershoot interrupt on the voltage slew. The value
programmed is the amount of eHPM (+ve) allowed after
reaching the optimum core voltage for the safe SoC
operation.
Bits
[7:0] Count for the wakeup delay.
Bits
[7:6] Read undefined. Write as zero.
[5:0] The time period for each count in the vddchkd and the
vddchk counters during the performance level change:
* set to 0x1D for 2μs when theapc_refclk_c clock is 15MHZ
* set to 0x3B for 2μs when the apc_refclk_c clock is
30MHZ.
Bits
[7:4] Read undefined. Write as zero.
[3:0] Programmable division to theapc_refclk_c clock
frequency for the PWI clock. The clock division is equal
to 2 * (APC_CLKDIV_PWICLK + 1).
Description
Minimum accumulated
00
01
10
11
Description
Description
Description
INTELLIGENT ENERGY MANAGEMENT
eHPM
0
4
16
31
Reset Value
0
0x0
0x0
Reset Value
0x00
Reset Value
0
0x00
Reset Value
0
0x0
2.5-33