Samsung S5PC100 User Manual page 384

S5PC100 USER'S MANUAL (REV1.0)
5.1
1 OVERVIEW
1.1 FEATURES
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Compatible with JEDEC specification of DDR2, mDDR and LPDDR2 SDRAM
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32bit data width only
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mDDR: up to 256Mbyte
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DDR2: up to 1Gbyte (8-bank) per 1 nCS (up to 1 nCS)
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LPDDR2: up to 256Mbyte
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Optimized pipeline stage for low latency
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QoS scheme to ensure low latency for some applications
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An advanced scheduler which enables efficient out-of order operations
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Excellent chip/bank interleaving and memory interrupting
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Adapts to various low power schemes to reduce the dynamic and static current of memory
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Outstanding exclusive accesses
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Bank selective precharge policy
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1:1 synchronous operation between AXI bus and memory interface
Note 1: Some DRAM's which are not compatible with the JEDEC specification can not be used as big as lised in the context.
DRAM CONTROLLER
1)
per 1 nCS (up to 2 nCS's)
1)
per 1 nCS (up to 2 nCS's)
DRAM CONTROLLER
5.1-1