Samsung S5PC100 User Manual page 242

S5PC100 USER'S MANUAL (REV1.0)
XXTI
DEEP _ STOP _ MODE
(internal )
XEINT [0 ]
( wakup event )
ARMCLK _ OFF
(internal )
ARMCLK
( internal )
APLL clock out
ARM _ ARESETn
(internal )
XnRSTOUT
( SFR _ OTHER [1:0 ] = 2 'b 10 )
APLL / MPLL /
HPLL / EPLL
( internal )
NOTE 1 . 1 ) OSC _ EN _ STOP = 1'b1 , 101 XXTI cycles .
2 ) OSC _ EN _ STOP = 1'b0 ,
NOTE 2 . 1 ) OSC _ EN _ STOP = 1'b1 , 1688 XXTI cycles .
2 ) OSC _ EN _ STOP = 1'b0 , 1688 XXTI cycles + delayed by OSC _ STABLE register .
NOTE 3 . 1 ) OSC _ EN _ STOP = 1'b1 , 145 XXTI cycles .
2 ) OSC _ EN _ STOP = 1'b0 , 145 XXTI cycles
Figure 2.4-14 DEEP-STOP Mode (TOP Domain Off) Wakeup Timing
8.5 SLEEP MODE WAKEUP
Figure 2.4-5 shows wakeup timing from SLEEP mode.
In SLEEP mode, XPWRRGTON becomes low and then external power (VDDINT/ARM/PLL) is off to minimize
leakage power of S5PC100. When SLEEP_WAKEUP is asserted, XPWRRGTON becomes high and then external
power is on. ARMCLK is supplied for ARM and ARM_ARESETn is released within some interval (refer to
XXTI 51 cycles
this interval can be adjusted by OSC
. . .
. . .
ARMCLK is the same as XXTI .
NOTE 1
NOTE 2
NOTE 3
+ delayed by OSC _ STABLE register .
Power Management
S / W sets P , M , S value
and enable APLL
PLL locking time ( 300 us)
Enabled by
S / W
. . .
_ STABLE register .
.
APLL clock out
2.4-43