Samsung S5PC100 User Manual page 786

MIPI DSIM
3.2.16 Read FIFO register (DSIM_RXFIFO, R, Address = 0xECB0_0x3C)
This register is the gate of FIFO read
DSIM_RXFIFO
RxDat
3.2.17 FIFO threshold level register (DSIM_FIFOTHLD, R/W, Address = 0xECB0_0x40 : hidden)
DSIM_FIFOTHLD
Reserved
WFullLevelSfr
8.7-30
Bit
[31:0] In Rx mode, user can read Rx data through this
register. Note that the CRC in the packet is not stored
in RxFIFO.
Bit
[31:9] Reserved
[8:0] Almost full level of SFR payload FIFO
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R
R/W Reset Value
-
R/W
Unknown
-
0x1FF