Samsung S5PC100 User Manual page 940

S5PC100 USER'S MANUAL (REV1.0) SD/MMC CONTROLLER
4.3 SD CLOCK STOP SEQUENCE
Figure 8.12-4 SD Clock Stop Sequence
The flow chart for stopping the SD Clock is shown in Figure 8.12-4. The Host Driver does not stop the SD Clock if
a SD transaction takes place on the SD Bus -- namely, when either Command Inhibit (DAT) or Command Inhibit
(CMD) in the Present State register is set to 1.
1. Set SD Clock Enable (ENSDCLK) in the Clock Control register to 0. After ENSDCLK is set, the Host
Controller stops SD Clock.
4.4 SD CLOCK FREQUENCY CHANGE SEQUENCE
Figure 8.12-5 SD Clock Change Sequence
The sequence for changing SD Clock frequency is shown in Figure 8.12-5. If SD Clock is still off, skip step (1).
The steps shown in Figure 8.12-5 are explained below:
1. Perform SD Clock Stop Sequence. Refer to 8.12.4.2
2. Perform SD Clock Supply Sequence. Refer to 8.12.4.3
8.12-5