Samsung S5PC100 User Manual page 149

S5PC100 USER'S MANUAL (REV1.0)
5.6.19 Wake-up Interrupt Pending Register16_23 (WKUP_INT_PEND16_23, R/W, Address =
0xE030_0F48)
Field
Reserved
WKUP_INT_PEND16_23[n]
Note. Even though WKUP_INT_MASK16_23[n] is masked, this register can be pended.
5.6.20 Wake-up Interrupt Pending Register24_31 (WKUP_INT_PEND24_31, R/W, Address =
0xE030_0F4C)
Field
Reserved
WKUP_INT_PEND24_31[n]
Note. Even though WKUP_INT_MASK24_31[n] is masked, this register can be pended.
5.7 EXTERN PIN CONFIGURATION REGISTERS IN POWER DOWN MODE
This registers keep their values during power down mode
5.7.1 Power Down Mode Pad Configure Register (PDNEN, R/W, Address = 0xE030_0F80)
Field Bit
Reserved [7:2]
PDNEN_CFG [1]
PDNEN [0]
Bit
[31:8]
This bit is set if WKUP_INT [n+16] is pending.
[n]
Writing '1' makes this bit clear. (n=0~7)
Bit
[31:8] Reserved
This bit is set if WKUP_INT [n+24] is pending.
[n]
Writing '1' makes this bit clear.(n=0~7)
Reserved
0 = Automatically by power down mode
1= by PDNEN bit
Power down mode pad state enable register.
If this bit is set to '1', external pins are controlled by power down mode
control register such as GPA0PDNCON, GPA0PDNPULL
1 = PADs Controlled by Power Down mode control registers
0 = PADs Controlled by normal mode
This bit automatically set to '1' if system enters into Power down mode
and write '0' to this bit or cold reset to clear. After wake up from Power
down mode, this bit maintains value '1' until writing '0'
Description
Reserved
Description
Description
PAD CONTRL
Reset Value
0
0
Reset Value
0
0
Reset Value
0
0
0
2.2-97