Samsung S5PC100 User Manual page 900

S5PC100 USER'S MANUAL (REV1.0)
DCFG Bit
DevSpd [1:0] Device Speed.
Indicates the speed at which the application requires the core to
enumerate, or the maximum speed the application supports.
However the actual bus speed is determined only after the chirp
sequence is complete, and is based on the speed of the USB host to
which the core is connected.
• 2'b00: High speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
• 2'b01: Full speed (USB 2.0 PHY clock is 30 MHz or 60 MHz)
• 2'b10: Low speed (USB 1.1 transceiver clock is 6 MHz).
If you select 6 MHz LS mode, you must do a soft reset.
• 2'b11: Full speed (USB 1.1 transceiver clock is 48 MHz).
Description
USB2.0 HS OTG
R/W Reset
Value
R/W 2'b0
8.10-57