Samsung S5PC100 User Manual page 533

CF CONTROLLER
5.2.10 ATA Software Reset (ATA_SWRST, R/W, Address = 0xE780_190C)
ATA_SWRST
Reserved
ata_swrst
5.2.11 ATA Interrupt Register (ATA_IRQ, R/W, Address = 0xE780_1910)
ATA_IRQ
Reserved [31:10]
ebi_abort_rd_int
ebi_abort_wr_int
ebi_bf_rd_int
ebi_bf_wr_int
mdma_hold_int
sbuf_empty_int
tbuf_full_int
atadev_irq_int
udma_hold_int
xfr_done_int
5.5-38
Bit
[31:1] Reserved
Software reset for the ATAPI host
0 = No reset
1 = Resets device registers and all registers of ATAPI
[0] host controller except CPU interface registers.
After software reset, to continue transfer, user must
configure all registers of host controller and device
registers.
Bit
Reserved
When ATAPI is aborted by EBI-BACKOFF signal, in
[9] case of read transfer (UDMA/MDMA class). CPU clears
this interrupt by writing "1".
When ATAPI is aborted by EBI-BACKOFF signal, in
[8] case of write transfer (UDMA/MDMA class). CPU clears
this interrupt by writing "1".
When EBI-BACKOFF signal is issued by EBI, In case of
[7] read transfer. If CFCON release the EBI BUS, this bit
clears automatically.
When EBI-BACKOFF signal is issued by EBI, in case of
[6] write transfer. If CFCON release the EBI BUS, this bit
clears automatically.
If ATAPI device makes pending in MDMA class. CPU
[5]
clears this interrupt by writing "1".
If source buffer is empty.
[4]
CPU clears this interrupt by writing "1".
If track buffer is half-full.
[3]
CPU clears this interrupt by writing "1".
If ATAPI device generates interrupt.
[2]
CPU clears this interrupt by writing "1".
If ATAPI device makes early termination in UDMA class.
[1]
CPU clears this interrupt by writing "1".
If all data transfers are complete.
[0]
CPU clears this interrupt by writing "1".
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
R
R/W
R/W Reset Value
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0