Samsung S5PC100 User Manual page 398

S5PC100 USER'S MANUAL (REV1.0)
3.1 PAD MUX FOR DRAM TYPE
PAD Name
64MB
Xm1ADDR[0] ADDR_0
Xm1ADDR[1] ADDR_1
Xm1ADDR[2] ADDR_2
Xm1ADDR[3] ADDR_3
Xm1ADDR[4] ADDR_4
Xm1ADDR[5] ADDR_5
Xm1ADDR[6] ADDR_6
Xm1ADDR[7] ADDR_7
Xm1ADDR[8] ADDR_8
Xm1ADDR[9] ADDR_9
Xm1ADDR[10] ADDR_10
Xm1ADDR[11] ADDR_11
Xm1ADDR[12]
Xm1ADDR[13]
Xm1ADDR[14] BA_0
Xm1ADDR[15] BA_1
Xm1CSn[1] CS_1
Xm1CSn[0] CS_0
Xm1CKE[1] CKE_1
Xm1CKE[0] CKE_0
NOTES:
1. If Number of Banks (MEMCONFIGn.chip_bank) is set 8 banks, Xm1CSn[1] is BA[2] bit.
2. If Number of Row Address Bits(MEMCONFIGn.chip_row) is set 15bits, Xm1CKE[1] is Addr[14].
Type field indicates whether pads are dedicated to the signal or pads are connected to the multiplexed signals.
mDDR
128MB 256MB
ADDR_0 ADDR_0
ADDR_1 ADDR_1
ADDR_2 ADDR_2
ADDR_3 ADDR_3
ADDR_4 ADDR_4
ADDR_5 ADDR_5
ADDR_6 ADDR_6
ADDR_7 ADDR_7
ADDR_8 ADDR_8
ADDR_9 ADDR_9
ADDR_10 ADDR_10
ADDR_11 ADDR_11
ADDR_12 ADDR_12
ADDR_13
BA_0 BA_0
BA_1 BA_1
CS_1 CS_1
CS_0 CS_0
CKE_1 CKE_1
CKE_0 CKE_0
LPDDR2
256MB 64MB
CA_0 ADDR_0 ADDR_0
CA_1 ADDR_1 ADDR_1
CA_2 ADDR_2 ADDR_2
CA_3 ADDR_3 ADDR_3
CA_4 ADDR_4 ADDR_4
CA_5 ADDR_5 ADDR_5
CA_6 ADDR_6 ADDR_6
CA_7 ADDR_7 ADDR_7
CA_8 ADDR_8 ADDR_8
CA_9 ADDR_9 ADDR_9
ADDR_10 ADDR_10
ADDR_11 ADDR_11
ADDR_12 ADDR_12
BA_0
BA_1
CS_1 CS_1
CS_2 CS_0
CKE_1 CKE_1
CKE_0 CKE_0
DRAM CONTROLLER
DDR2
128MB 256MB 512MB
ADDR_0 ADDR_0
ADDR_1 ADDR_1
ADDR_2 ADDR_2
ADDR_3 ADDR_3
ADDR_4 ADDR_4
ADDR_5 ADDR_5
ADDR_6 ADDR_6
ADDR_7 ADDR_7
ADDR_8 ADDR_8
ADDR_9 ADDR_9
ADDR_10 ADDR_10
ADDR_11 ADDR_11
ADDR_12 ADDR_12
ADDR_13
BA_0 BA_0
BA_1 BA_1
1)
CS_1 BA_2 BA_2
CS_0 CS_0
CKE_1
CKE_0 CKE_0 CKE_0
1GB
ADDR_0
ADDR_1
ADDR_2
ADDR_3
ADDR_4
ADDR_5
ADDR_6
ADDR_7
ADDR_8
ADDR_9
ADDR_10
ADDR_11
ADDR_12
ADDR_13
BA_0 BA_0
BA_1 BA_1
1) 1)
BA_2
CS_0 CS_0
2)
ADDR_14
CKE_0
5.1-15