Samsung S5PC100 User Manual page 922

S5PC100 USER'S MANUAL (REV1.0)
8.2.55 Power and Clock Gating control register (PCGCCTL, R/W, Address = 0xED20_0E00)
The application uses this register to control OTG's clock gating.
DIEPTSIZ0 Bit
Reserved [31:1]
StopPclk [0]
-
STOP Pclk
The application sets this bit to stop the PHY clock if the USB is
suspended, the session is not valid, or the device is
disconnected. The application clears this bit if the USB is
resumed or a new session starts.
Description
USB2.0 HS OTG
R/W Reset Value
31'h0
R/W 1'b0
8.10-79