Samsung S5PC100 User Manual page 461

ONENAND CONTROLLER
4.32 SYNCHRONOUS WRITE ENABLE REGISTER (SYNC_WRITE, R, ADDRESS = 0XE710_0280)
SYNC_WRITE
Reserved
Sync_Wr
4.33 CACHE READ ENABLE REGISTER (CACHE_READ, R/W, ADDRESS = 0XE710_0290)
CACHE_READ
Reserved
Cache_Rd
5.3-24
Bit
[31:1] Reserved
Synchronous write enable. Set by software during
initialization.
If this bit is not set, the controller assumes that the device
connected does not support synchronous writes. Therefore, if
this bit is clear but the host tries to program the configuration
register of the flash device with the sync_write bit enabled to
"1", the controller masks the value of the sync_write bit prior to
sending the configuration register information to the
OneNAND Flash memory device. In this setting, any writes to
the OneNAND Flash memory device are sent in asynchronous
[0]
mode.
If this bit is set, the controller writes configuration register
information as programmed. Therefore, if the host enables the
"sync_write" bit in configuration register, the controller sends
all future writes to the device as synchronous writes.
0 = Not supported. The "Sync_Write" bit of the configuration
register is masked. All writes are in asynchronous mode.
1 = Supported. If the "Sync_Write" bit of the configuration
register is set, all writes is performed as synchronous writes.
Bit
[31:1] Reserved
Cache read enable. Set by software during initialization.
If this bit is clear, the controller assumes that the OneNAND
Flash memory device does not support cache read/ write
operations and ignores any MAP10 pipelined commands. The
subsequent MAP01 operations are treated as normal reads
[0]
and writes.
If this bit is set, the controller accepts all MAP10 pipelined
commands and process them as expected.
0 = Not supported
1 = Supported
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Reset Value
Device
Dependent
Reset Value
Device
Dependent