Samsung S5PC100 User Manual page 343

S5PC100 USER'S MANUAL (REV1.0)
3.4
1 ASYNC BRIDGE OVERVIEW
1.1 ABOUT THE AXI ASYNCHRONOUS BRIDGE
The AXI asynchronous bridge (AsyncAxi) enables two AXI clock domains to communicate. Figure 3.4-1 shows
AsyncAxi with data being transferred between two AXI clock domains.
The bridge provides buffered synchronization of the AXI channels:
AW Write Address Channel.
W Write Data Channel.
B Write Response Channel.
AR Read Address Channel.
R Read Data Channel.
The major features of the bridge include:
•
Single independent AXI master and AXI slave interfaces
•
All AXI channels are buffered independently
•
Configurable FIFO buffer depth for each AXI channel
•
Dynamic Synchronous Bypass mode. (S5PC100 does not use Bypass mode)
ASYNC BRIDGE
Figure 3.4-1 Asynchronous Bridge Block Diagram
ASYNC BRIDGE
3.4-1