Samsung S5PC100 User Manual page 862

S5PC100 USER'S MANUAL (REV1.0)
8.2.2 OTG PHY Clock Control Register (OPHYCLK, R/W, address = 0xED30_0004)
OPHYCLK
Reserved [31:7] -
serial_mode
xo_ext_clk_enb
common_on_n
Reserved
id_pullup
clk_sel
Bit
[6] UTMI/ Serial Interface Select
If this register is asserted, USB traffic flows through the serial
interface.
• 1'b0: Data on the D+ and D- lines is transmitted and
received through the UTMI.
• 1'b1: Data on the D+ and D- lines is transmitted and
received through the USB1.1 Serial Interface.
[5] Reference Clock Select for XO Block
• 1'b0: External crystal
• 1'b1: External clock/ Oscillator
[4] Force XO, Bias, Bandgap, and PLL to Remain Powered
During a Suspend
This bit controls the power-down signals of sub-blocks in the
Common block if the USB 2.0 OTG PHY is suspended.
• 1'b0 : 48MHz clock on clk48m_ohci is available at all times,
except in Suspend mode.
• 1'b1 : 48MHz clock on clk48m_ohci is available at all times,
even in Suspend mode.
[3] -
[2] Analog ID Input Sample Enable
• 1'b0 : id_dig disable.
• 1'b1 : id_dig enable. (The id_dig output is valid, and within
20ms, id_dig must indicate the type of plug connected.)
[1:0] Reference Clock Frequency Select for PLL
• 2'b00 : 48MHz
• 2'b01 : Reserved
• 2'b10 : 12MHz
• 2'b11 : 24MHz
Description
USB2.0 HS OTG
R/W Reset Value
25'h0
R/W 1'b0
1'b0
R/W
R/W 1'b0
1'b0
R/W 1'b0
R/W 2'b00
8.10-19