Samsung S5PC100 User Manual page 982

S5PC100 USER'S MANUAL (REV1.0)
9.14 CLOCK CONTROL REGISTER
Clock Control Register
•
CLKCON0, R/W, Address = 0xED80_002C
•
CLKCON1, R/W, Address = 0xED90_002C
•
CLKCON2, R/W, Address = 0xEDA0_002C
At the initialization of the Host Controller, the Host Driver sets the SDCLK Frequency Select according to the
Capabilities register.
CLKCON Bit
SELF [15:8] SDCLK Frequency Select
REQ
This register is used to select the frequency of SDCLK pin. The frequency is
not programmed directly; rather this register holds the divisor of the Base
Clock Frequency For SD Clock in the Capabilities register. Only the
following settings are allowed.
Setting 00h specifies the highest frequency of the SD Clock. Setting multiple
bits, the most significant bit is used as the divisor. But multiple bits must not
be set. The two default divider values are calculated by the frequency that is
defined by the Base Clock Frequency For SD Clock in the Capabilities
register.
(1) 25MHz divider value
(2) 400kHz divider value
According to the SD Physical Specification Version 1.01 and the SDIO Card
Specification Version 1.0, maximum SD Clock frequency is 25MHz, and
never exceeds this limit.
The frequency of SDCLK is set by the following formula:
Clock Frequency = (Base Clock)/ divisor
Therefore, select the smallest possible divisor which results in a clock
frequency that is less than or equal to the target frequency.
For example, if the Base Clock Frequency For SD Clock in the
Capabilities register has the value 33MHz, and the target frequency is
25MHz, then selecting the divisor value of 01h yields 16.5MHz, which is the
nearest frequency less than or equal to the target. Similarly, to approach a
clock value of 400kHz, the divisor value of 40h yields the optimal clock value
of 258kHz.
80h base clock divided by 256
40h base clock divided by 128
20h base clock divided by 64
10h base clock divided by 32
08h base clock divided by 16
04h base clock divided by 8
02h base clock divided by 4
01h base clock divided by 2
00h base clock (10MHz-63MHz)
Description
SD/MMC CONTROLLER
Reset Value
0
8.12-47