Samsung S5PC100 User Manual page 355

S5PC100 USER'S MANUAL (REV1.0)
If the AXI interconnect's arbitration scheme is priority base and Async Bridge has highest priority, Async Bridge is
handled as a default master. In that case, the AXI interconnect can give WREADY signal to default master 1 cycle
earlier than to other masters. If Async Bridge is default master, AWVALID signal should be delayed 1 more cycle
to increase bandwidth capacity of write data channel.
Table 3.4-1 The Delay Cycle for Various Burst Transactions and the Clock Combinations
Clock & Index
D1/D0 Master
Clock Rate Clock
200:166 200.0
166:133 166.7
133:100 133.3
100:66 100.0
66:33 66.7
Slave Async
4
Clock Index
166.7 1 -1.4
133.3 2 -1.3
100.0 3 -1
66.7 4 -0.5
33.3 5 1
Bubble Size
8 12 16
-0.6 0.2 1
-0.3 0.7 1.8
0.3 1.7 3
1.5 3.5 5.5
5 9 13
ASYNC BRIDGE
Delay Cycle
4 8 12
0 0 1
0 0 1
0 1 2
0 2 4
1 5 9
16
1
2
3
6
13
3.4-13