Samsung S5PC100 User Manual page 395

DRAM CONTROLLER
To calculate the DDR2 rd_fetch value:
rd_fetch DDR2) = INT((Delay + 0.5T + 0.25T)/T) = INT(Delay/T + 0.75),
Delay: board delay + PHY input/output delay, T: clock period, INT(x): the rounded-up integer value of x
Therefore, rd_fetch must have minimum one value.
T0
CK
SDRAM command
DQS
DQ
90' phase shifted DQS
PHY read input FIFO
AXI read channel
An LPDDR/LPDDR2 does not have an internal DLL. Without an internal DLL as you may see in Figure 5.1-7, the
data is sent out after tDQSCK before the read latency is over. Even if we assume zero delay, since tDQSCK
becomes relatively large in high frequencies, the read fetch cycle should be set to one.
T0
CK
SDRAM command
DQS
DQ
90' phase shifted DQS
PHY read input FIFO
AXI read channel
If a delay exists such as Figure 5.1-8, a bigger value should be assigned to rd_fetch.
5.1-12
T1 T2 T3
READ
RL = 3
RL + rd_fetch = 4
Figure 5.1-7 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, zero delay, RL=3, rd_fetch=1)
T1 T2 T3
READ
RL = 3
RL + rd_fetch = 5
Figure 5.1-8 Timing Diagram of Read Data Capture
(LPDDR/LPDDR2, non-zero delay, RL=3, rd_fetch=2)
T4 T5
tDQSCK
negedge negedge
sampling sampling
Q0 Q1 Q2 Q3
{Q1, Q0}
T4 T5
Delay
tDQSCK
negedge
sampling
Q0 Q1
S5PC100 USER'S MANUAL (REV1.0)
T6 T7
{Q3, Q2}
{Q1, Q0} {Q3, Q2}
T6 T7
negedge
sampling
Q2 Q3
{Q1, Q0} {Q3, Q2}
{Q1, Q0} {Q3, Q2}
T8
T8