Samsung S5PC100 User Manual page 653

S5PC100 USER'S MANUAL (REV1.0)
8.2
1 OVERVIEW
The S5PC100 RISC microprocessor supports a multi-master I
(SDA) and an Serial Clock Line (SCL) carry information between bus masters and peripheral devices which are
2
connected to the I C -bus. The SDA and SCL lines are bi-directional.
2
In the multi-master I C-bus mode, multiple microprocessors receive or transmit serial data to or from slave
devices. The master S5PC100 initiates and terminates a data transfer over the I
S5PC100 uses Standard bus arbitration procedure.
To control multi-master I
• 2
Multi-master I C-bus control register- I2CCON
•
2
Multi-master I C-bus control/status register- I2CSTAT
•
2
Multi-master I C-bus Tx/Rx data shift register- I2CDS
• 2
Multi-master I C-bus address register- I2CADD
2
If the I C-bus is free, the SDA and SCL lines should be both at High level. A High-to-Low transition of SDA
initiates a Start condition. A Low-to-High transition of SDA initiates a Stop condition while SCL remains steady at
High Level.
The master device always generates Start and Stop conditions. A 7-bit address value in the first data byte, which
is put onto the bus after the Start condition has been initiated, can determine the slave device which the bus
master device has selected. The 8th bit determines the direction of the transfer (read or write).
Every data byte put onto the SDA line should be eight bits in total. There is no limit send or receive bytes during
the bus transfer operation. Data is always sent from most-significant bit (MSB) first, and every byte should be
immediately followed by acknowledge (ACK) bit.
2
I C-BUS INTERFACE
2
C-bus operations, values must be written to the following registers:
2
C-bus serial interface. A dedicated Serial Data Line
2
C-bus. The I
2
I C-BUS INTERFACE
2
C-bus in the
8.2-1