Samsung S5PC100 User Manual page 486

S5PC100 USER'S MANUAL (REV1.0)
7.11 NFCON STATUS REGISTER (NFSTAT, R/W, ADDRESS = 0XE720_0028)
NFSTAT
Flash_RnB_GRP
RnB_TransDetect
_GRP
Reserved
Flash_nCE[3:0]
(Read-only)
MLCEncodeDone
MLCDecodeDone
IllegalAccess
RnB_TransDetect
Flash_nCE[1]
(Read-only)
Flash_nCE[0]
(Read-only)
Reserved
Flash_RnB
(Read-only)
Bit
The status of RnB[3:0] input pin.
[31:28]
0 = NAND Flash memory busy
1 = NAND Flash memory ready to operate
If RnB[3:0] low to high transition is occurs, this field is set. To
clear this write '1'.
[27:24] 0 = RnB transition is not detected
1 = RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[23:12] Reserved
[11:8] The status of nCE[3:0] output pin
If 4-bit ECC or 8-bit ECC encodng is finished, this field is set
and issues interrupt. The NFMLCECC0 and NFMLCECC1 have
[7]
valid values. To clear this, write '1'.
1 = 4-bit ECC or 8-bit ECC encoding is completed
If 4-bit ECC or 8-bit ECC decoding is finished, this field set and
issues interrupt. The NFMLCBITPT, NFMLCL0 and NFMLCEL1
[6]
have valid values. To clear this, write '1'.
1 = 4-bit ECC or 8-bit ECC decoding is completed
Once Soft Lock or Lock-tight is enabled, The illegal access
(program, erase) to the memory set this bit.
[5] 0 = illegal access is not detected
1 = illegal access is detected
To clear this value, write 1 to this bit.
If RnB low to high transition occurs, this field is set and issues
interrupt. To clear this write '1'.
[4] 0 = RnB transition is not detected
1 = RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[3] The status of nCE[1] output pin
[2] The status of nCE[0] output pin
[1] Reserved
The status of RnB input pin.
[0]
0 = NAND Flash memory busy
1 = NAND Flash memory ready to operate
Description
NAND FLASH CONTROLLER
Reset Value
0x0
0x800
0x0
0
0
0
1
1
1
0
1
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