Samsung S5PC100 User Manual page 388

S5PC100 USER'S MANUAL (REV1.0)
2.1.3 DDR2
1. To provide stable power for controller and memory device, the controller must assert and hold CKE to a logic
low level. Then apply stable clock. Note: XDDR2SEL should be High level to hold CKE to low.
2. Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock
frequency. Set the PhyControl0.ctrl_dll_on bit-field to '1' to turn on the PHY DLL.
3. DQS Cleaning: Set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to correct value
according to clock frequency and memory tAC parameters.
4. Set the PhyControl0.ctrl_start bit-field to '1'.
5. Set the ConControl. At this moment, an auto refresh counter should be off.
6. Set the MemControl. At this moment, all power down modes should be off.
7. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register.
8. Set the PrechConfig and PwrdnConfig registers.
9. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC
parameters.
10. If QoS scheme is required, set the QosControl0~7 and QosConfig0~7 registers.
11. You must wait for the PhyStatus0.ctrl_locked bit-fields to change to '1'. Check whether PHY DLL is locked.
12. PHY DLL compensates the changes of delay amount caused by Process, Voltage and Temperature (PVT)
variation during memory operation. Therefore, it should not be off for reliable operation. It can be off except
runs at low frequency. If off mode is used, set the PhyControl0.ctrl_force bit-field to correct value according
to the PhyStatus0.ctrl_lock_value[9:2] bit-field for fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-
field to turn off PHY DLL.
13. Confirm whether stable clock is issued minimum 200us after power on
14. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
15. You must wait for minimum 400ns.
16. Issue a PALL command using the DirectCmd register.
17. Issue an EMRS2 command using the DirectCmd register to program the operating parameters.
18. Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
19. Issue an EMRS command using the DirectCmd register to enable the memory DLLs.
20. Issue a MRS command using the DirectCmd register to reset the memory DLL.
21. Issue a PALL command using the DirectCmd register.
22. Issues two Auto Refresh commands using the DirectCmd register.
23. Issues a MRS command using the DirectCmd register to program the operating parameters without resetting
the memory DLL.
24. Wait for minimum 200 clock cycles.
25. Issue an EMRS command using the DirectCmd register to program the operating parameters. If OCD
calibration is not used, issue an EMRS command to set OCD Calibration Default. After that, issue an EMRS
command to exit OCD Calibration Mode and to program the operating parameters.
26. If there are two external memory chips, perform steps 14~25 for chip1 memory device.
27. Set the ConControl to turn on an auto refresh counter.
28. If power down modes are needed, set the MemControl register.
DRAM CONTROLLER
5.1-5