Samsung S5PC100 User Manual page 356

ASYNC BRIDGE
3 REGISTER DESCRIPTION
Register
HALFSYNC
ASYNC_INDEX
DMASTER
NOTE: If async bridge has highest priority in AXI interconnect, then async bridge is handled as a default master.
3.1 HALFSYNC REGISTER (HALFSYNC, R/W, 0XE340_0000)
HALFSYNC
Reserved
HALFSYNC SEL
3.2 ASYNCINDEX REGISTER (ASYNCINDEX, R/W, 0XE340_0004)
ASYNCINDEX
Reserved
ASYNC_INDEX
3.3 DMASTER REGISTER (DMASTER, R/W, 0XE340_0008)
Name
Reserved
DEFAULT_MASTER
NOTE: All SFR can be programmed at anytime
3.4-14
Address R/W
0xE340_0000 R/W
0xE340_0004 R/W
0xE340_0008 R/W
Bit
[31:1] Reserved
[0] 0 = Using 1 cycle synchronizer
1 = Using 1/2 cycle synchronizer
Bit
[31:3] Reserved
0 = D0 clock : D1 clock = 1: 1 & W channel BW improve off
1 = D0 clock : D1 clock = 6: 5 & W channel BW improve on
2 = D0 clock : D1 clock = 5: 4 & W channel BW improve on
[2:0]
3 = D0 clock : D1 clock = 4: 3 & W channel BW improve on
4 = D0 clock : D1 clock = 3: 2 & W channel BW improve on
5 = D0 clock : D1 clock = 2: 1 & W channel BW improve on
Bit
[31:1] Reserved
0 = Optimizing AW channel delay to non-default master
[0]
1 = Optimizing AW channel delay to default master
Description
1/2 cycle synchronizer selection
Async index register for write enhancing
Optimizing delay for default master
Description
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
Reset Value
Reset Value
Reset Value
Reset Value
0x00
0x00
0x00
0
0
0
0x0
0
0x0