Samsung S5PC100 User Manual page 495

NAND FLASH CONTROLLER
7.25 MLC 8-BIT ECC ERROR PATTEN REGISTER (NFMLC8BITPT0, R, ADDRESS = 0XE720_0060)
NFMLC8BITPT0
th
4 Error bit pattern
rd
3 Error bit pattern
nd
2 Error bit pattern
st
1 Error bit pattern
7.26 MLC 8-BIT ECC ERROR PATTEN REGISTER (NFMLC8BITPT1, R, ADDRESS = 0XE720_0064)
NFMLC8BITPT1
th
8 Error bit pattern
th
7 Error bit pattern
th
6 Error bit pattern
th
5 Error bit pattern
7.27 NFCON ACCESS TIMING ADJUSTMENT REGISTER (NFACTADJ, R/W, ADDRESS = 0XE720_0068)
NFACTADJ
Reserved
NFACTADJ
5.4-30
Bit
th
[31:24]
4 Error bit pattern
rd
[23:16] 3 Error bit pattern
nd
[15:8] 2 Error bit pattern
st
[7:0] 1 Error bit pattern
Bit
th
[31:24]
8 Error bit pattern
th
[23:16] 7 Error bit pattern
th
[15:8] 6 Error bit pattern
th
[7:0] 5 Error bit pattern
Bit
[31:1] Reserved
0 : HCLK =< 133MHz
[0]
1 : HCLK => 166MHz
S5PC100 USER'S MANUAL (REV1.0)
Description
Description
Description
Reset Value
0x00
0x00
0x00
0x00
Reset Value
0x00
0x00
0x00
0x00
Reset Value
0x00
0x0