Clock Controller - Samsung S5PC100 User Manual

S5PC100 USER'S MANUAL (REV1.0)
2.3
1 CLOCK DOMAIN
S5PC100 consists of three bus parts. First part consists of Cortex A8, D0_BUS and D0_BUS-attached modules.
Cortex A8 supports only synchronous mode so that Cortex A8 and D0_BUS must operate synchronously.
Second part consists of D1_BUS and D1_BUS-attached modules. Final part, D2 domain, is for low-power audio
play.
D0 domain operates at up-to 166MHz clock, D1 domain operates at up-to 133MHz (D1 domain has many
multimedia IPs which can be synthesized under 133MHz.). D2 domain operates at up-to 80MHz. All 3 parts
communicate asynchronously.
( up - to 166MHz)

CLOCK CONTROLLER

D 0 domain
Cortex A 8 ,
DMA, SECSS
D0_ BUS
Memory &
File system
Async
bridge
D 2 domain
( up - to 80MHz)
D2_ BUS
Figure 2.3-1 S5PC100 Clock Domain
D 1 domain
( up - to 133MHz)
Muti- media IPs
Async
bridge
D1_ BUS
Async
bridge
APBs
CLOCK CONTROLLER
2.3-1