Samsung S5PC100 User Manual page 674

S5PC100 USER'S MANUAL (REV1.0)
4.2.3 SPI FIFO Control Register
•
MODE_CFG0, R/W, Address = 0xEC30_0008
•
MODE_CFG1, R/W, Address = 0xEC40_0008
•
MODE_CFG2, R/W, Address = 0xEC50_0008
MODE_CFGn
CH_WIDTH
TRAILING_CNT
BUS_WIDTH
RX_RDY_LVL
TX_RDY_LVL
Reserved
RX_DMA_SW
TX_DMA_SW
DMA_TYPE
** Channel Transfer size must be smaller than Bus Transfer size or the same as.
4.2.4 Slave Selection Signal Control Signal
•
CS_REG0, R/W, Address = 0xEC30_000C
•
CS_REG1, R/W, Address = 0xEC40_000C
•
CS_REG2, R/W, Address = 0xEC50_000C
CS_REGn
NCS_TIME_COUNT
Reserved
AUTO_N_MANUAL
NSSOUT
Bit
[30:29] 00 = Byte
10 = Word
[28:19] Count value from writing the last data in RX FIFO to flush
trailing bytes in FIFO
00 = Byte
[18:17]
10 = Word
[16:11] Rx FIFO trigger level in INT mode. Trigger level is from 0 to 63.
The value means byte number in RX FIFO
[10:5] Tx FIFO trigger level in INT mode. Trigger level is from 0 to 63.
The value means byte number in TX FIFO
[4:3] Reserved
[2] Rx DMA mode enable/disable
0 = Disables DMA Mode
[1] Tx DMA mode on/off
0 = Disables DMA Mode
[0] DMA transfer type, single or 4 busts.
0 = single
DMA transfer size must be set as the same size in SPI DMA.
Bit
NSSOUT inactive time =
[9:4]
((nCS_time_count+3)/2) x SPICLKout
[3:2] Reserved
Chip select toggle manual or auto selection
[1]
0 = Manual
Slave selection signal (manual only)
[0]
0 = Active
Description
01 = Halfword
11 = Reserved
01 = Halfword
11 = Reserved
1 = Enables DMA Mode
1 = Enables DMA Mode
1 = 4 burst
Description
1 = Auto
1 = Inactive
SPI CONTROLLER
Reset Value
0
0
0
0
0
-
0
0
0
Reset Value
0
-
0
1
8.3-9