Samsung S5PC100 User Manual page 193

S5PC100 USER'S MANUAL (REV1.0)
10.5.9 Control HCLKD1 / PCLKD1 Clock Gating 2 (Connectivity) (CLK_GATE_D1_4, R/W, Address =
0xE010_0530)
D1 domain connectivity system clock gating
CLK_GATE_D1_4
Reserved
CLK_HSIRX
CLK_HSITX
CLK_CCAN1
CLK_CCAN0
CLK_IRDA
CLK_SPI2
CLK_SPI1
CLK_SPI0
CLK_HDMI_IIC
CLK_IIC
CLK_UART3
CLK_UART2
CLK_UART1
CLK_UART0
Bit
[31:14] Reserved
[13] Gating PCLK for MIPI_HSI receiver (0: mask, 1: pass)
Gating PCLK for MIPI_HSI transmitter
[12]
(0: mask, 1: pass)
[11] Gating PCLK for CCAN1 (0: mask, 1: pass)
[10] Gating PCLK for CCAN0 (0: mask, 1: pass)
[9] Gating PCLK for IRDA (0: mask, 1: pass)
[8] Gating PCLK for SPI2 (0: mask, 1: pass)
[7] Gating PCLK for SPI1 (0: mask, 1: pass)
[6] Gating PCLK for SPI0 (0: mask, 1: pass)
[5] Gating PCLK for IIC for HDMI (0: mask, 1: pass)
[4] Gating PCLK for IIC (0: mask, 1: pass)
[3] Gating PCLK for UART3 (0: mask, 1: pass)
[2] Gating PCLK for UART2 (0: mask, 1: pass)
[1] Gating PCLK for UART1 (0: mask, 1: pass)
[0] Gating PCLK for UART0 (0: mask, 1: pass)
Description
CLOCK CONTROLLER
Reset Value
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2.3-43