Samsung S5PC100 User Manual page 231

Power Management
mode, the S5PC100 explicitly adds the crystal oscillator settle-down time (the wait-time is programmed using
OSC_STABLE registers) after wake-up from the STOP mode.
(VDD_INT= 1.2V± 0.05V, TA = -40 to 85°C, VDD_SYS0 = 3.3V ± 0.3V, 2.5V ± 0.2V, 1.8V ± 0.1V)
Parameter
VDD_IO to VDD_ALIVE
VDD_ALIVE to VDD_INT/VDD_ARM
VDD_ARM to PWR_EN(PWRRGTON)
VDD_INT/VDD_ARM to Oscillator stabilization
Oscillator stabilization to nRESET & nTRST high
External clock input high level pulse width
External clock to HCLK (without PLL)
HCLK (internal) to CLKOUT
HCLK (internal) to SCLK
Reset assert time after clock stabilization
APLL, MPLL Lock Time
EPLL Lock Time
Sleep mode return oscillation setting time.
The interval before CPU runs after nRESET is
released.
NOTE : 2. Sleep mode return oscillation setting time depends on the value in the PWR_STABLE register.
2.4-32
Table 2.4-13 Clock Timing Constants
Symbol
tOA
tAE
tOSC
tOR
t
EXTHIGH
t
EX2HC
t
HC2CK
t
HC2SCLK
t
RESW
t
(2)
t
OSC2
t
RST2RUN
S5PC100 USER'S MANUAL (REV1.0)
Min
0
tAI 1
1
10
1
25
5
4
2
4
-
PLL
-
4
2
5
Typ Max
10
cycle
-
10
10
8
XTIpll or
-
EXTCLK
300
300
XTIpll or
19
2
EXTCLK
XTIpll or
-
EXTCLK
Unit
ms
us
ns
us
ns
ns
ns
ns
us
us