Samsung S5PC100 User Manual page 776

MIPI DSIM
3.2.4 Time Out register (DSIM_TIMEOUT, R/W, Address = 0xECB0_0x0C)
DSIM_TIMEOUT
Reserved
BtaTout
LpdrTout
3.2.5 Configuration register (DSIM_CONFIG , R/W, 0xECB0_0x10)
This register configures MIPI DSI master such as data lane number, input I/F, porch area, frame rate, BTA, LPDT,
ULPS, etc.
DSIM_CONFIG
Reserved
TxTypeSfr
SyncInform
BurstMode
VideoMode
8.7-20
Bit
[31:24] Reserved
[23:16] Timer for BTA
This register specifies time out from BTA request to
change the direction with respect to Tx escape clock.
[15:0] Timer for LP Rx mode timeout
This register specifies time out on how long RxValid
keeps deasserted after RxLpdt asserts with respect to
Tx escape clock.
RxValid is Rx data valid indicator.
RxLpdt is an indicator that D-phy is under RxLpdt
mode.
RxValid and RxLpdt is signal from D-phy.
Bit
[31:29] Reserved
[28] Packet Header data in SFR FIFO transmitting type
0 = If SFR packet header FIFO is not empty,
1 = If SFR Payload FIFO is filled over threshold level,
Transmits Packet Header.
Set threshold level via DSIM_FIFOTHLD
register(Base_addr + 0x44)
[27] Sync Pulse or Event mode select in Video mode
0 = Event mode (non burst, burst)
1 = Pulse mode (non burst only)
In command mode, this bit is ignored.
[26] Burst mode in Video mode
In Non-burst mode, RGB data area is filled with RGB
data and Null packets according to input bandwidth of
RGB I/F.
In Burst mode, RGB data area is filled with RGB data
only.
0 = Non-burst mode
1 = Burst mode
In command mode, this bit is ignored.
[25] Display configuration
0 = Command mode
1 = Video mode
Description
Description
S5PC100 USER'S MANUAL (REV1.0)
R/W Reset Value
-
R/W
R/W
R/W Reset Value
-
R/W
R/W
R/W
R/W
-
0xFF
0xFFFF
-
0
0
0
1