Samsung S5PC100 User Manual page 626

UART
Peripheral BUS
8.1-2
Transmitter
Transmit Buffer
Register(64 Byte)
Transmit Shifter
Control Buad-rate
Unit Generator
Receiver
Receive Shifter
Receive Buffer
Register(64 Byte)
In FIFO mode, all 64 Byte of Buffer register are used as FIFO register.
In non-FIFO mode, only 1 Byte of Buffer register is used as Holding register.
Figure 8.1-1 UART Block Diagram
S5PC100 USER'S MANUAL (REV1.0)
Transmit FIFO Register
(FIFO mode)
Transmit Holding Register
(Non-FIFO mode)
Clock Source
Receive Holding Register
(Non-FIFO mode only)
Receive FIFO Register
(FIFO mode)
TXDn
RXDn